RVI System Architecture
A high-level RVI system architecture comprises both hardware and software sub-systems.
The hardware includes a standard personal computer and the Reconfigurable Instrument (RI) connected to it through a physical connection. The connection allows the reconfiguration of the RI as well as the exchange of information between the PC and the RI. The information exchanged can be data, commands, error messages, or acknowledgement messages.
The software related to the PC is called Computer Software (CS) and the code corresponding to the FPGA of the RI is called Synthesizable Hardware Description Code (SHDC). The CS is responsible for the user interface, the port management, and eventually a few offline data elaboration programs and utilities. The SHDC is responsible for the management of the physical connection with the PC, the ADC and DAC operations, data generation and acquisition, real-time online data processing (arithmetic, compression, filtering…), and on-board real time mass data handling (storage, retrieving, fetching…).
RVI Hardware System
Reconfigurable Instrument (RI)
The RI includes one mother board (the RVI main board) and two daughter boards. The mother board is built around a medium to large capacity FPGA device (ACTEL A3PE 600/1500/3000) and four main blocks, namely: a block of communication ports, an extension memory, debugging facilities and miscellaneous components, and two high quality board-to-board connectors with 54 pins directly connected to the FPGA general purpose I/Os.
Four standard communication ports are logically connected to the FPGA: RS232, USB1.2, USB2.0, and Ethernet 10/100. The main board has a SODIMM 144STD socket for SDRAM modules from 128 MB to 512MB. For debugging purposes, the main board also counts on four push-buttons (one denounced for manual clocking), four LEDs, and a four-digit seven-segment LCD display; all attached to the FPGA.
The first daughter board, a Low Performance Daughter Board (LP-DB), contains a dual channel 10-bits 20 MSPS Analog-to-Digital Converter (AD9201, Analog Devices), a dual channel 14-bit 1 MSPS Digital-to-Analog Converter (LTC1654, Linear). The second daughter board, a High Performance Daughter Board (HP-DB) contains a single channel 14-bits 125 MSPS Analog-to-Digital Converter (LTC2255, Linear), a single channel 16-bit 50 MSPS Digital-to-Analog Converter (LTC1668, Linear). Both boards have signal conditioning circuits to accept and generate AC and DC signals in different ranges as described in the following table:
Also, both daughter boards have one generic digital I/O for triggering, a general purpose digital extension connector, and a high quality board to board connector allowing the daughter boards to be directly plugged into the RVI main board.
Optionally, the RI could count on an on-board mass storage SDRAM memory to expand the FPGA memory capacity. This can be used for real time data acquisition or other fast applications where the bandwidth of the physical connection is not sufficient to rely on the PC memory. Other miscellaneous components include a crystal oscillator, a small (PLD device) circuit to switch the physical connection between communication and configuration modes.
RVI Block-Level Global Software Architecture
The Computer Software (CS)
The computer software is a collection of independent modules hierarchically organized. Each module operates on standardized files (buffers) containing all relevant information including data, commands, and error messages. In the RVI system, time critical operations are carried out in the RI while non critical operations are processed by the PC. Basically, the CS provides:
- A generic RVI graphical and textual user interface.
- A Library of virtual instruments with custom user interfaces.
- Data storage facilities.
- Automatic physical communication control (drivers).
Optionally, the CS could also provide additional services such as:
- An internet connection for remote instrument control and operation.
- Specific data analysis packages and other facilities.
- A friendly interface with a general purpose in-chip logic analyzer for development and debugging.
Synthesizable Hardware Description Code (SHDC)
The SHDC is essentially a synthesis friendly VHDL description divided into four basic blocks: A port communication module, a dual port memory and registers to communicate with the core, the instrument core, and an FPGA port assignment (and other constraints) description file. Optionally, the SHDC could include an external SDRAM module controller, an on chip logic analyzer and stimuli generator modules for debugging and development, and physical as well as timing constraints files.
The port communication module supports the basic protocol of the connection and, at a higher level, an RVI specific protocol to handle the RI. The communication between the PC and the Core Instrument is done in two ways. The first is by reading and writing data into the dual port memory. The PC accesses the memory from one port and the Core Instrument from the other port. The second way is by reading and writing into registers. Some registers are read-only for the Core Instrument and others are read-only for the PC. A few registers are reserved to handle the RVI communication protocol. Therefore, these are not available for generic use.
Depending on the nature of the port and the core instrument, the RI may send an interrupt signal to the PC to trigger a specific action. Also, the PC can do polling on specific registers to check whether there’s a request for a given action. The PC may also use registers to pass signals and parameters to the core instrument. The exchange of signals through registers could be used to implement a semaphored mechanism for the simultaneous access to the dual port memory or to regulate the access to the external memory unit.
Integrating a Reconfigurable Instrument Core in an RVI system
In order to integrate a reconfigurable instrument core in an RVI system it must comply with the standardized interfaces of the PC-FPGA communication block and the external hardware specific interface block. It should also comply with a common mechanism of interaction. If the three main blocks: PC-FPGA communication block, instrument core, and the external hardware interface respect both previous conditions, then each block can be updated or upgraded independently and can be reused in different contexts. The interfaces and the mechanism of interaction depend on the complexity and performance of the overall system. In order to define an Open Standard for an RVI system based on FPGA, several important factors must be considered:
- Expected evolution of FPGA devices in terms of Logic capacity.
- Special resources.
- External hardware availability such as (daughter/mezzanine boards with ADCs, DACs, FPAAs, cables, connectors).
- Possible PC communication ports (PP, USB, Serial, Ethernet, etc.)
- Software tools: Synthesizers, FPGA programming tools, Simulation and Debugging tools, Ad Hoc tools (GUI, High Level RVI design capture and synthesis, on chip logic analyzers).
- Quantity and quality of targeted instruments.
- Portability, updatability and upgradeability of the system and/or any of its subsystems (Software, Operating System, PC ports, FPGA families, external hardware, etc).
Architecture for Single Instruments - Implementation Examples
GUI for a Wave Form Generator
General Purpose Debugging Interface
Designing New Complex Instruments
Most of the software involved in the above virtual instrumentation examples can be reused for many other core instruments without modification. The hardware is simply reconfigured to turn it into a different instrument. Moreover, the availability of general purpose debugging interfaces as shown above, greatly simplifies the process. Such interfaces allow reading and writing from and into the registers and memory of the communication block, as well as downloading or uploading data between the FPGA and the PC. Such interface was validated with an APA150 and an APA300.
The above figure depicts a block diagram of the next level of FPGA implementation for a more complex Reconfigurable Virtual Instrumentation system that is currently being implemented in the RVI Main Board. The internal RVI bus allows exchanging data between the PC/FPGA communication block and each of the other blocks having a common interface. In our implementation, we will be using the Wishbone interconnection standard, which is already present on many available open-cores. For critical communication, we foresee point-to-point fast dedicated connections. The highlighted parts show a possible concrete implementation for two instruments: a Low Performance Arbitrary Waveform Generator and a Low Performance Digital Oscilloscope, with a display controller for debugging and monitoring. The RVI Controller block receives commands from the PC to performance direct memory access data transfers between the DP memory and any block and between any two blocks connected to the common bus.
Architecture for Multiple Instruments
By promoting an open source/open core1 approach with the RVI project, we allow a large community of users/contributors to rely on all developed materials, saving important costs of commercial IP blocks. It will also be possible to modify the cores in order to adapt them to different situations for optimal performance. In general all benefits of open source software apply to an RVI system like the one proposed here, contributing socially and economically through a sustainable development. We expect from the RVI system to stimulate the intellectual property production with a high technological content and a very low financial investment since, in this case, the manpower is the dominant cost.
While the cost of the RVI hardware is expected to remain approximately constant, its value will strongly increase with each new virtual instrument that can be implemented through the RVI platform. An easy updateability and upgradeability of the system will mitigate the obsolescence of the hardware, while the portability will allow an expansion of the potential users/developers base. After an initial global architecture proposal, the open source approach will allow the developers to evolve towards better open standards that facilitate the interchangeability and interoperability of the different software and hardware building blocks.